The escalating demands for high density and performance associated with semiconductor devices require small design features, high reliability, and increased manufacturing throughput. As design features continue to shrink, the latchup effect becomes more prevalent in semiconductor devices.
The latchup effect creates a low resistance path between the positive and negative voltage supplies of a Complementary Metal Oxide Semiconductor (CMOS) circuit and enables the flow of large currents through the affected circuit. When latchup occurs, the circuit stops functioning and may even be destroyed because of the heat developed by the large currents. Therefore, designers seek to control or eliminate the latchup effect.